1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as an LSI, in particular, relates to a semiconductor integrated circuit having a scan circuit arranged therein.
2. Description of the Related Art
A semiconductor integrated circuit such as an LSI conventionally has a scan circuit therein which is arranged for the purpose of determining whether the semiconductor integrated circuit has a defect formed in a manufacturing process or not. For instance, Japanese Patent Application Laid-Open No. S63-134970 and Japanese Patent Application Laid-Open No. H04-072583 describe a testing technique with the use of the scan circuit.
The scan circuit uses a scan flip-flop (hereafter referred to as an FF) as shown in FIG. 5, for instance.
FIG. 5 illustrates a configuration for forming a scan-FF by using a flip-flop (hereafter referred to as an FF) provided with a reset terminal.
A multiplex function (MUX) is added to an input (D) of the above described FF with the reset terminal. The R-FF (flip-flop with reset terminal) can make the multiplex function select a normal data input (D) when a scan enable signal is logic zero, and a scan data (SI) when the scan enable signal is logic one, and can employ the input as the input (D) of the R-FF.
FIG. 6 illustrates a conventional example of adding a scan circuit using the scan-FF to a semiconductor integrated circuit.
FIG. 6 illustrates a configuration which has scan-FFs 602 to 609 arranged for an input/output signal of an internal circuit 601 of a semiconductor integrated circuit 600. When a scan enable signal SE shows logic zero, data is input from normal data input terminals IN1 to IN4; and an internal circuit operates to output a processing result in the internal circuit to normal data output terminals OUT1 to OUT4.
On the other hand, when a scan enable signal shows logic one, scan-FFs 602 to 609 set scan data SI as an input source and form a shift register configuration (scan chain). The scan-FFs 602 to 609 shifting-output the data, and then, the test result can be observed from a scan data output SO.
A scan test consists of two operations. The first operation is to set the above described scan enable signal at logic one, and set an arbitrary data value to scan-FFs 602 to 605 (scan shift operation).
The next operation is to set the scan enable signal at logic zero, make the internal circuit operate by using the above described set data value, and make the scan-FFs 606 to 609 capture a processing result (scan capture operation).
The scan test is performed by alternately repeating the above described two operations.
In FIG. 6, the scan-FF606 has further a reset terminal R. This reset terminal R is controlled by an internal logic circuit in a normal operation.
However, in a scan test, the reset terminal is configured to reset the above described scan-FF606 by its signal so as to prevent the scan-FF606 from unintentionally being reset.
Specifically, the above semiconductor integrated circuit 600 has a multiplexer 610 arranged in an input section for the reset terminal R of the scan-FF606, and sets a scan mode at logic one during scan test.
As described above, it becomes easy to determine whether the internal circuit works well or not, by arranging a scan circuit and freely reading and writing a data value retained in an FF in the semiconductor integrated circuit. However, on the other hand, the following malfunctions may occur in an LSI which treats security data such as a cryptogram.
1. It is possible to draw out security data by reading out a data value for the FF.
2. It is possible to rewrite the security data by writing a different data value.
3. It is possible to control an internal memory unit (RAM), and read and write the data by operating the data value for the FF.
A conventional example for preparing the above situation will be shown which is a semiconductor integrated circuit that prevents security data stored in an LSI from being read out or rewritten by fraudulent means and simultaneously can test the semiconductor integrated circuit by using a scan circuit.
There is Japanese Patent Application Laid-Open No. 2004-117029 which is a Japanese patent and is shown in FIG. 7, as the above described conventional example.
FIG. 7 does not illustrate a circuit system corresponding to an internal circuit 601 shown in FIG. 6, namely, a logic circuit system to be used in a normal operation. In other words, FIG. 7 illustrates only a site directly relating to a scan circuit which has enhanced the security function.
The semiconductor integrated circuit has a circuit 707 which observes a condition of a scan mode signal that switches between a normal operation mode and a test mode of testing the semiconductor integrated circuit by using a scan circuit, and resets a data value of an FF when a scan mode state changes.
The semiconductor integrated circuit also has an access disabling unit 718 for disabling access into an internal RAM while the above described mode signal shows a test mode.
The semiconductor integrated circuit further has an output control unit 715 provided with a dummy FF which outputs supplied data in the test mode and inhibits the output of the supplied data in the normal operation mode.
As described above, a configuration in FIG. 7 shows the following effect.
FIG. 8 illustrates a waveform chart showing the operation.
In FIG. 8, the circuit 707 produces a signal of detecting both edges in response to a scan mode signal which selectively designates a test mode and a normal operation mode; and when the signal of detecting both edges and a reset input from the outside satisfy the AND logic, resets an FF which forms a scan chain in each initiating time and terminating time of a scan test.
Accordingly, the circuit 707 can prevent data in a normal operation mode from being drawn when the mode has migrated from a normal operation to a scan test operation, and from being changed through a normal operation by changing the mode with the use of data written in an FF during the scan test operation.
The circuit 700 also masks an internal XCE signal which is controlled in an internal circuit, by using a scan mode signal; thereby disables the access to a memory unit such as a RAM during a scan test by using the scan test operation; and further prevents readout from the memory unit through a scan chain, or writing of an arbitrary value into the memory unit through the normal operation.
Furthermore, the circuit 700 does not supply a clock to a dummy FF in a normal operation mode; thereby disables shifting-output by a scan chain; and accordingly also prevents readout on a value of an internal FF by changing only the scan enable signal during the normal mode and using the scan chain.
However, an integrated circuit configuration in the conventional example has the following problems.
(1) When the circuit enlarges the scale and increases the number of an FF, but prepares a scan test by one scan chain, the scan test needs a long time in proportion to the number of the FF.
Then, in order to shorten a testing period of time, there is a configuration of arranging a plurality of scan chains for forming parallel lines. But the configuration needs an output control unit with the use of the dummy FF in a number corresponding to the scan chains, and enlarges a circuit scale.
(2) A scan mode signal for selectively designating a normal operation mode and a test mode is prepared for preventing a scan test from unintentionally being set or reset, as shown in a scan-FF606 of FIG. 6, for instance.
However, the scan mode signal is not necessary for a configuration of an integrated circuit using scan-FFs that can be directly controlled by a reset terminal, as shown in a scan-FF605 of FIG. 6
In spite of it, the integrated circuit in the conventional example can not remove the mode signal in order to disable the access to an internal memory during a scan test, and consequently needs to increase the number of terminals.
(3) There is a configuration of an integrated circuit which does not always need an FF with a non-synchronous set terminal or an FF with a reset terminal, in order to realize a function of a normal operation.
Furthermore, an integrated circuit often avoids the use as much as possible, in order to minimize a circuit scale.
However, in order to reset an FF when a mode signal changes, it is necessary to use an FF with a non-synchronous set terminal and an FF with a reset terminal even for an FF which does not need them in a normal operation, and consequently to enlarge a circuit scale.
The present invention is directed at solving the problems.